diff --git a/references.bib b/references.bib
index 54dde28..f14ff7b 100644
--- a/references.bib
+++ b/references.bib
@@ -9445,3 +9445,12 @@ pages={89--100},
 year={2009},
 organization={IEEE}
 }
+
+@incollection{tiwari2014modeling,
+title={Modeling the Impact of Reduced Memory Bandwidth on HPC Applications},
+author={Tiwari, Ananta and Gamst, Anthony and Laurenzano, Michael A and Schulz, Martin and Carrington, Laura},
+booktitle={Euro-Par 2014 Parallel Processing},
+pages={63--74},
+year={2014},
+publisher={Springer}
+}
diff --git a/system_methodology.tex b/system_methodology.tex
index 074b109..bc9e197 100644
--- a/system_methodology.tex
+++ b/system_methodology.tex
@@ -45,7 +45,8 @@ frequency and voltage; we extended Gem5 DVFS to incorporate memory frequency
 scaling. As shown in Figure~\ref{fig-system-block-diag}, Gem5 provides a DVFS
 controller device that provides an interface to control frequency by the OS at
 runtime. We developed a memory frequency governor similar to existing Linux CPU
-frequency governors.
+frequency governors. Timing and current parameters of DRAM are scaled with its
+frequency as described in the technical note from Micron~\cite{micronpower-TN-url}.
 %that are capable of tuning memory frequency at runtime. 
 The blocks that we added or significantly modified from Gem5's original
 implementation are shaded in Figure~\ref{fig-system-block-diag}.