Commit 5611d5db5c975d22cc8e07e2d5fde3da1d205a60

Authored by Rizwana Begum
1 parent a160460b

some more comments

references.bib
@@ -9445,3 +9445,12 @@ pages={89--100}, @@ -9445,3 +9445,12 @@ pages={89--100},
9445 year={2009}, 9445 year={2009},
9446 organization={IEEE} 9446 organization={IEEE}
9447 } 9447 }
  9448 +
  9449 +@incollection{tiwari2014modeling,
  9450 +title={Modeling the Impact of Reduced Memory Bandwidth on HPC Applications},
  9451 +author={Tiwari, Ananta and Gamst, Anthony and Laurenzano, Michael A and Schulz, Martin and Carrington, Laura},
  9452 +booktitle={Euro-Par 2014 Parallel Processing},
  9453 +pages={63--74},
  9454 +year={2014},
  9455 +publisher={Springer}
  9456 +}
system_methodology.tex
@@ -45,7 +45,8 @@ frequency and voltage; we extended Gem5 DVFS to incorporate memory frequency @@ -45,7 +45,8 @@ frequency and voltage; we extended Gem5 DVFS to incorporate memory frequency
45 scaling. As shown in Figure~\ref{fig-system-block-diag}, Gem5 provides a DVFS 45 scaling. As shown in Figure~\ref{fig-system-block-diag}, Gem5 provides a DVFS
46 controller device that provides an interface to control frequency by the OS at 46 controller device that provides an interface to control frequency by the OS at
47 runtime. We developed a memory frequency governor similar to existing Linux CPU 47 runtime. We developed a memory frequency governor similar to existing Linux CPU
48 -frequency governors. 48 +frequency governors. Timing and current parameters of DRAM are scaled with its
  49 +frequency as described in the technical note from Micron~\cite{micronpower-TN-url}.
49 %that are capable of tuning memory frequency at runtime. 50 %that are capable of tuning memory frequency at runtime.
50 The blocks that we added or significantly modified from Gem5's original 51 The blocks that we added or significantly modified from Gem5's original
51 implementation are shaded in Figure~\ref{fig-system-block-diag}. 52 implementation are shaded in Figure~\ref{fig-system-block-diag}.